A system on a chip (SOC) generally includes at least one processing core, which generally is operatively coupled to a level 2 (L2) memory cache. Various core bus agents included in the processing core, the L2 cache, and various other components of the SOC are usually interconnected through a bus interface unit (BIU). However, the L2 cache may have a bandwidth and a frequency requirement that is different from one or more other components of the SOC. For example, the L2 cache may operate on a clock signal that has a different frequency compared to a frequency of a clock signal of the processing core. Such differences in the bandwidth and/or frequency requirement between the L2 cache and other components accessing the BIU may create additional challenges while designing the SOC.
The description in this section is related art, and does not necessarily include information disclosed under 37 C.F.R. 1.97 and 37 C.F.R. 1.98. Unless specifically denoted as prior art, it is not admitted that any description of related art is prior art.